This invention relates to a multi-processor system provided with a plurality of processors and in particular to a load balancing control method and a device for realizing the same, which are suitable to balance loads applied to the plurality of processors as uniformly as possible, when the processors are so constructed that they are loosely coupled with each other.
Various methods for ameliorating processing characteristics of an electronic computer system by combining a plurality of processors have been proposed and brought into practice. The following are representative examples of such system constructions:
(1) a tightly coupled multi-processor system, whose processors have a main memory in common, and
(2) a loosely coupled multi-processor system constructed by processors, each of which is provided with a main memory exclusively used, are generally known.
In the two representative multi-process system constructions described above, the tightly coupled multiprocessor system indicated in (1) is efficacious for ameliorating processing characteristics for the real time processing (known as the on-line real time processing). On the other hand the loosely coupled multi-processor system indicated in (2) is efficacious for increasing batch processing characteristics, i.e. increasing the throughput. Recently, the loosely coupled multi-processor system indicated in (2) is utilized more and more widely from the viewpoint of increasing reliability of the electronic computer system. This may be due to the fact that, in the case of the loosely coupled multi-processor system, even if trouble is produced in either one of the processors constituting the multi-processor system and the processor is stopped, service of the whole electronic computer system is not stopped, if it is so controlled that the processor carries out no work (job).
On the other hand, with the recent remarkable development of utilization of electronic computer systems, needs for on-line processing such as TSS (Time Sharing System) apart from batch processing increase. Consequently, it is desired to ameliorate characteristics of on-line processing represented by TSS processing under a loosely coupled multi-processor system construction aiming at increasing batch processing characteristics.
This leads to realizing a control method permitting to balance loads applied to processors in a multi-processor structure as uniformly as possible.
One of the prior art techniques for the load balancing control method for a multi-processor system in the on-line processing such as TSS processing is disclosed in Japanese Patent Unexamined Publication No. 59-157778. The load balancing control method disclosed in that publication will be explained below briefly, referring to FIG. 1. According to the load balancing control method disclosed in FIG. 2, in a structure provided with processors CP.sub.0, CP.sub.1 and a memory CM common to the processors, in which each of communication control processors SP.sub.0 --SP.sub.n is connected to each of the processors CP.sub.0, CP.sub.1 and terminals A, B and so forth are connected to each of the communication control processors SP.sub.0 --SP.sub.n, the load status of each of the processor is stored as e.sub.0, e.sub.1 in the common memory CM; and finally the number n.sub.1 of the last load processor is stored therein. A server's memory SM.sub.0, SM.sub.1 is disposed in each of the communication control processors SP.sub.0 --SP.sub.n and in SM.sub.0 are set the called status processor number n.sub.a corresponding to the terminal A and the called status processor number n.sub.b corresponding to the terminal B.
In this construction, by setting permanently the number of the processor, which is the least frequently used, at n.sub.1, when data has been once transferred from the terminal A to the terminal B, the communication control processor SP.sub.0 searches the called status processor number n.sub.a (supposed to be 0 here) corresponding to the terminal A from the server's memory SM.sub.0 and demands a connection process to the processor CP.sub.0. The processor CP.sub.0, which has received the demand, sets a call between the terminal A and the terminal B through the processor SP.sub.0 and changes the called status processor number in the processor SP.sub.0 to n.sub.b =0. When the data transfer between the terminals A and B is terminated, the processor SP.sub.0 searches n.sub.a =0 and n.sub.b =0 corresponding to the terminals A and B, respectively, from the memory SM.sub.0 and demands a disconnecting process to the processor CP.sub.0.
Now, supposing that n.sub.1 =0 has been set, the processor CP.sub.0 disconnects the call, which has been set between the terminals A and B; at the same time searches the last load processor number n.sub.1 =0 in the common memory CM and set the called status processor numbers n.sub.a and n.sub.b in the server's memory SM.sub.0 equal to the last load processor number n.sub.1 =0. In this way, when the terminal B is called at the next time, the processor SP.sub.0 demands a connecting process to the processor CP.sub.0, which is lightly loaded.
The load balancing control method is thus realized. However the method disclosed in the abovementioned Japanese Patent Unexamined Publication No. 59-157778 is realizable only in a tightly coupled multi-processor system construction and no control method realizable in a loosely coupled multi-processor system is disclosed therein. Further the control method disclosed in the above-mentioned publication can be realized by the fact that the system is provided with a memory common to processors.